Micron plans 42 Gb/mm2 NAND density for late 2027 launch

Micron expects to begin mass production of its G11 NAND flash memory in the second half of 2027. The new technology targets a storage density of 42 Gb/mm2, which is double the 21 Gb/mm2 capacity of its current G9 generation in triple-level-cell form. This density increase surpasses the next-generation products from competitors Kioxia and Samsung.

The chip will also boost input/output speeds from 3,600 MT/s to 5,400 MT/s. That represents a 50% increase in data transfer rates. Additionally, the energy required to move each bit of data will drop by more than 25%. These improvements aim to support high-capacity solid-state drives for clients and data centers, as well as storage devices designed for artificial intelligence workloads.

A key engineering shift in G11 involves wafer-on-wafer bonding. Micron will fabricate the memory array and the peripheral circuitry on separate wafers. Each wafer uses a manufacturing process optimized for its specific function. The company then bonds these two wafers together. This method differs from its previous CMOS-under-array designs, which integrated the logic and memory on a single substrate.

Scott DeBoer, Micron's president and chief technology and products officer, confirmed the bonding approach at a company event this week. He stated that G11 is the world's most advanced NAND. DeBoer said the timing was right to introduce the technology because it became cost-effective and relevant to product specifications.

The design will exceed 400 layers. Micron has not disclosed the exact number of active wordline layers or memory decks. The company says the design features an industry-leading memory cell pitch. This suggests the density gain comes from both added layers and smaller cell dimensions. More technical details are expected in 2027, closer to the start of high-volume production.

Beyond G11, Micron plans to continue scaling in three dimensions. The company is developing high-mobility materials and ultra-dense cell architectures. These advancements aim to improve transistor characteristics and reduce energy consumption within the chip. DeBoer noted that the industry is scaling by adding layers and shrinking cell dimensions.