SMIC and CXMT Absorb Rising Costs as EUV Restrictions Force Multi-Step DUV Production

Chinese semiconductor firms are paying a higher price for every layer of silicon they produce under export controls that block access to extreme ultraviolet lithography machines.

Morgan Stanley estimates that CXMT, a major Chinese DRAM manufacturer, currently produces only about one-third as many bits per wafer as its Western competitors. The bank labeled lithography access a "hard ceiling" for Chinese memory development in a June report. This efficiency gap stems from the reliance on deep ultraviolet equipment, which requires multiple exposure steps to achieve densities that EUV tools handle in a single pass.

Chris Mack, co-founder and CTO of Fractilia, explained that industry standards previously suggested three exposures on a 193 immersion tool cost roughly the same as one EUV exposure. However, at four masks, EUV becomes the more economical option. Each additional pattern requires precise alignment with previously etched layers. This process accumulates overlay errors and increases process variation, leading to more defects and longer production times. Designers often add extra space around features to compensate, which enlarges the chip size and reduces the number of usable dies per wafer.

The financial impact is substantial because wafers cost tens of thousands of dollars each. Mack noted that manufacturers sell dies, not wafers, making the reduction in output per wafer a direct cost driver. While SMIC has successfully produced the Kirin 9000S processor on a 7nm-class process without EUV, and its newer Kirin 9030 shows movement toward 5nm density, these chips still trail the leading processes from TSMC and Samsung. Analysts suggest the technology gap between China and the West remains five years or more due to these constraints.

DUV technology still has limitations but offers a viable path for certain applications. Micron developed its 1-alpha DRAM without EUV, and Morgan Stanley believes CXMT can achieve a similar milestone for HBM3e. Douglas Fuller, a researcher at Copenhagen Business School, expects advanced packaging to support DUV-based DRAM through the end of the decade. Nevertheless, Micron transitioned to EUV for its 1-gamma DRAM to secure more than 30% greater bit density. Mack stated he would be "hard pressed" to believe 3nm or 2nm logic nodes could be economically viable without EUV. Morgan Stanley projects that CXMT will increase its global DRAM bit supply share from 14% in 2026 to 16% in 2028 by adding new production capacity, despite the continued cost premiums.